1. Field of the Invention
This invention relates to the field of integrated circuits. More particularly, this invention relates to integrated circuits having a plurality of serially connected test cells for applying a test stimulus to an integrated circuit and for capturing a test response.
2. Description of the Prior Art
It is known to provide integrated circuits having a scan chain of test cells to examine the internal state of the integrated circuit and to test external logic. An example of such scan chains is the JTAG system described in the IEEE 1149.1 1990 specification.
A scan chain consists of a storage element (test cell) adjacent to each of an integrated circuit's inputs and outputs connected together like a shift register. These scan chains may be boundary scan chains arranged between an integrated circuit and its input/output pads, macrocell scan chains arranged around a macrocell within an integrated circuit or an internal scan chain associated with points within the core or other working circuitry of an integrated circuit. All three of these types of scan chain may be separately provided or a single scan chain may have elements of more than one type.
FIG. 1 of the accompanying drawings illustrates a boundary scan chain. Each JTAG style test cell 2 is disposed adjacent an associated input/output contact pad 4 to which mechanical connections to the integrated circuit package may be made. It will be appreciated that test cells 2 may be associated with points within the integrated circuit that are not directly associated with a contact pad 4 providing that the test cells 2 still form part of a serial scan chain.
Using this technique test stimulus data is serially loaded into the test cells 2 via a serial input 6. When this test stimulus data is in position it is applied to the appropriate points within the integrated circuit. The integrated circuit is then allowed to conduct one or more processing cycles following which the signal values at the points coupled to the test cells 2 are captured. These captured signal values are then serially clocked out from the scan chain via a serial output 8 for analysis. In this way, a test stimulus can be applied and the resulting output values captured and compared against expected results. This is a powerful technique for testing integrated circuits, particularly embedded macrocells where external access to all the signals is not available.
FIG. 2 of the accompanying drawings illustrates a test cell 2 (configured for an input line) in more detail. The serial data path passes through a serial input line 10, an input transmission gate 12, a first latch 14, an output transmission gate 16, a second latch 18 and a serial output line 20. The first latch 14 and the second latch 18 comprise inverting buffers using weak feedback followed by a further inverter to restore the signal polarity. The serial loading of data through the test cells operates by the use of separate clock signals for the input transmission gate 12 mad the output transmission gate 16. The input transmission gate 12 is enabled by an input clock signal shelf that occurs before a non-overlapping output clock signal shclk2 fed to the output transmission gate 16. In this way, a signal value from a preceding test cell 2 is first loaded into the first latch 14 via the serial input line 10 whilst the signal value that had been held by the test cell 2 under consideration is output from the second latch 18 to the succeeding test cell via the serial output line 20. After this transfer has occurred, the input transmission gates 12 are disabled and the output transmission gates 16 enabled to transfer the signal value from the first latch 14 to the second latch 18.
The data path to the integrated circuit in normal system operation, passes through a contact pad 4, a main path transmission gate 22 and an output line 24. A stimulate transmission gate 26 and a capture transmission gate 28 are also coupled to the output line 24. The stimulate transmission gate 26 acts in conjunction with the main path transmission gate 22 under control of a multiplexing signal muxct1 to either apply the signal value at the contact pad 4 to the integrated circuit or the signal value currently output from the first latch 14. The capture transmission gate 28 acts under control of a capture signal capclk to apply the current signal on the output line 24 to the input of the first latch 14 where it is stored for subsequent serial output and analysis.
The above described stimulate and capture functions are only some of the uses of the JTAG system. The scan chain is conventionally only used during predetermined hardware test operations.
Another aspect of the development of systems incorporating integrated circuits is the design and development of computer programs. Computer programs inevitably contain errors that require a software developer to trace and fix. In order to assist the software developer in this task, it is usual to provide a breakpoint during the program execution whereby the programmer can establish a set of conditions under he wishes the execution of the program to stop so that the variables present at that time can be examined to determine how the program is functioning. An example of such breakpoints would be "stop when an instruction is fetched from a certain location", or "stop every time a branch occurs".
The identification and handling of such breakpoints by analysis of the address bus, the data bus or control signals is normally performed external to the integrated circuit itself. This is because the amount of logic required to perform the comparison is too large to be conveniently borne by the integrated circuit itself. Also, the external logic must perform the comparison at high speed, due to cross-chip delays and skew between the signals of differing buses.
In addition to the predetermined hardware test operation discussed above it is also desirable to study the hardware operation in a more dynamic manner when searching for particular hardware conditions that may be giving rise to problems.